The module is breadboard compatible via a 15-pin 0.1" male header connector.
The design is open source (licenced under Creative Commons) and the design files (schematic, gerbers, bill of materials and drillfiles etc) will be made available on this page soon.
This work is licensed under a Creative Commons Attribution-ShareAlike 3.0 Unported License.
Here's a few photos...
|Bare boards provided by Laen's PCB Order / DorkBotPDX out of Oregon USA.|
|Screenshot of the PCB Layout in Diptrace|
- Four 131,072 x 8 bit Parallel SRAM chips in logical parallel configuration. Meaning all data lines and address lines are shared by all four SRAM chips. This is an optimisation biased towards the reading or writing of 32-bit values - this requires only a single address assertion for the entire 32 bit operation.
- Even though the unit is optimised for 32-bit block accesses, every individual byte in the entire 512KB addressable space is individually accessible if needed.
- At time of writing (2012/02/12) maximum known random access write speed is 1.54Megabytes per second, when using a Parallax Propeller (P8X32A-D40) chip using PLL16X multiplier and a 5MHz external crystal oscillator. In other words this memory can be written (or read, the operations are equal in speed terms) from top to bottom in around 0.34 seconds. I am still working on code improvements that should yield further speed optimisations, these will be published on this page in due course.
- This performance is a compromise between high speed of access and low number of IO pins required to drive the module. The SRAM chips have a 17-bit address space which is accessed using only 9 GPIO pins on the microcontroller. This is achieved by latching the low 8 bits, then latching the next 8 bits and finally asserting the last bit as a straight-through from the microcontroller to the SRAMs. Full information about how to write memory drivers (for any platform) will be given in the "Notes for Developers" section on this page.
- This memory module can be used with any microcontroller, there is no "minimum speed" requirement to drive this memory, but the maximum speed is effectively limited by the propagation delays in the ICs on the memory module.
- The module has a "Write Protected" state, which prevents accesses to the latches and the SRAM chips - meaning that it is possible to use the 9 data lines (from the microcontroller) to be used as GPIO while still retaining data undisturbed in the memory module.
- This memory module would be suitable for buffering high sampling rate audio data, or even certain low-middle resolutions of VGA pixel data.
- Compact layout: The current PCB design is 2.8" long by 1.2" wide (71mm by 30mm), It is a four-layer PCB with components fitted to both sides, total depth excluding the male header connector is 0.29" (7.4mm).
- Four 0.12" (3mm) diameter mounting holes.
DOWNLOAD THE DESIGN FILES
This download contains the Gerber files, Bill Of Materials, drillfile and also the original Diptrace (v184.108.40.206) EDA design files.
Version 1.0 CC-BY-SA3.0 512KB SRAM Module by ANW
Updated (2012-02-23) The above download link has been updated to add DXF documents (Schematics and PCB Layers) and also netlist files for both "Mentor" and "Pads" EDA packages.
NOTES FOR DEVELOPERS
(Coming soon, sorry for the delays. It will be done by the end of Sunday at the latest!)
MANY THANKS TO...
- Laen's PCB Order, affiliated with DorkbotPDX. - Without whom I would never have been able to get this far with the design and never in a sensible budget or timeframe. Thanks for your help Laen!
- http://forums.parallax.com - I'm very grateful to this brilliant support forum for the rather magnificent Parallax Propeller development and hacking platform. Link to the forums page for this project.
- CR, HS and SS. You know who you are. Every day is a learning experience with you guys.
DISCLAIMER (Disclaimer itself is modified from the one used by "Dangerous Prototypes" under the CC-BY-SA license http://dangerousprototypes.com/disclaimer/)
These designs are offered under various open source licenses, with the following additional terms and conditions:
Indemnity. Licensee will indemnify and hold Adam N. Ward and his related entities harmless for, from and against, any claims or liabilities, including without limitation product liability claims, arising out of the use, reproduction or distribution of Software, Hardware, Documentation and parts thereof.
Limited Warranty and Limited Liability. THE SOFTWARE, HARDWARE AND DOCUMENTATION IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. Adam N. Ward disclaims all responsibility for the accuracy or reliability of the Software, Hardware and Documentation and does not warrant they will meet licensee’s requirements, be uninterrupted or error-free, or that any defects in the Software, Hardware or Documentation will be corrected. The entire risk arising out of use or performance of the Software, Hardware and Documentation provided under this Agreement is assumed by Licensee.
In no event shall Adam N. Ward be liable for any incidental, special, indirect or consequential damages, lost profits or lost data, cost of procurement of substitute goods, technology or services, any claims by third parties (including but not limited to any defense thereof), any claims for indemnity or contribution, or other similar costs, whether asserted on the basis of contract, tort (including negligence), breach of warranty, or otherwise. IN ANY EVENT, ADAM N. WARD’S LIABILITY UNDER THIS AGREEMENT AND FOR THE SOFTWARE, HARDWARE AND DOCUMENTATION IS LIMITED TO THE AMOUNT LICENSEE PAID ADAM N. WARD FOR THE SOFTWARE, HARDWARE AND/OR DOCUMENTATION.